rus
Issue #7/2024
A.V. Strogonov, O. Bordyuzha, A.I. Strogonov
INTERNATIONAL EXPERIENCE IN DEVELOPING RISC-V PROCESSOR CORES AND OPEN SOURCE SOFTWARE TOOLS FOR THEIR DESIGN
INTERNATIONAL EXPERIENCE IN DEVELOPING RISC-V PROCESSOR CORES AND OPEN SOURCE SOFTWARE TOOLS FOR THEIR DESIGN
DOI: 10.22184/1992-4178.2024.238.7.156.164
The article examines the experience of developing RISC-V processor cores for commercial use by the example of processors from MIPS, SiFive, Alibaba Cloud Intelligence, as well as academic projects Rocket Chip from the University of California at Berkeley and XiangShan from the Chinese Academy of Sciences.
Tags: machine instruction set microprocessor core multi-cluster system multi-issue pipeline risc-v architecture scalable ip processor архитектура risc-v масштабируемый ip-процессор микропроцессорное ядро многоканальный конвейер мультикластерная система система машинных команд
Subscribe to the journal Electronics: STB to read the full article.
The article examines the experience of developing RISC-V processor cores for commercial use by the example of processors from MIPS, SiFive, Alibaba Cloud Intelligence, as well as academic projects Rocket Chip from the University of California at Berkeley and XiangShan from the Chinese Academy of Sciences.
Tags: machine instruction set microprocessor core multi-cluster system multi-issue pipeline risc-v architecture scalable ip processor архитектура risc-v масштабируемый ip-процессор микропроцессорное ядро многоканальный конвейер мультикластерная система система машинных команд
Subscribe to the journal Electronics: STB to read the full article.
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